The IC 24LC01/24LC02 uses the I2C addressing proto- col and 2-wire serial interface which includes a bidirec- tional serial data bus synchronized by a clock. Microchip 24LC02 EEPROM are available at Mouser Electronics. Mouser offers inventory, pricing, & datasheets for Microchip 24LC02 EEPROM. Description, Bit/Bit Serial EePROM Write Protect Memory Chips. Company, Pronics. Datasheet, Download 24LC02 datasheet. Quote. Find where to.
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During data transfer, the data line must remain stable whenever the clock line is high. Instead, after the EEPROM ac- knowledges the receipt of the first data word, the microcontroller can transmit up to seven more data words. Once the stop condition for a write command has been issued from the master, the device initiates the internally timed write cycle.
24LC02 Datasheet(PDF) – Ceramate Technical
Data Input Hold Time. If not, the chip will return to a standby state. If the device is still busy with the.
Search field Part name Part description. Stresses exceeding the range specified under “Absolute Maxi. The device is optimized for use in many industrial and com.
For relative timing, refer to timing diagrams. Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete this feature can be used to maximize bus throughput.
Upon receipt of this ad- dress, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. Hardware controlled write protection. Data transfer may be initiated only when the. Output Capacitance See Note.
Clock and data transition. These are 24lv02 ratings only. After this period the first clock pulse is generated. Commerical temperature range 0. The device address word consist of a mandatory one, zero sequence for the first four most significant bits refer to the diagram show- ing the Device Address.
Time in which the bus must be free before a new transmission can start. Partial page write allowed. Serial clock data input. Data Input Setup Time. Output Valid from Clock. Input Capacitance See Note.
ACK polling can be initiated immediately. Internally organized with 8-bit words, the 2K requires an 8-bit data word address for random word addressing. The higher data word address bits are not incremented, re- taining the memory page row location refer to Page write timing. These three datasheet must compare to their corresponding hard-wired input pins. This happens during the ninth clock cycle.
The SDA pin is bidirectional for serial data transfer. Datwsheet page write is initiated the same as byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Internally organized with 8-bit words, the 1K requires a 7-bit data word address for random word addressing.
The microcontroller must terminate the page write sequence with a stop condition. The pin is open-drain driven and may be wired-OR with any number of other open-drain or open collector devices. Characteristics Functional Description Timing Diagrams.
24LC02 Datasheet, PDF – Alldatasheet
After receiving the 8-bit data word, the EEPROM will output a zero and the address- ing device, such as a microcontroller, must terminate the write sequence with a stop con- dition. A read operation is initi- ated if this bit is high and a write operation is initiated if this bit is low.
Write operation with built-in timer. Functional operation of datasheet device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. A write operation requires an 8-bit data word address following the device address word and acknowledgment.